RISC-V

Data Alignment

In RISC-V assembly, data alignment ensures that data variables are stored at memory addresses that are multiples of their data size (called natural alignment).While the core RISC-V specification allows unaligned memory accesses, many hardware implementations do not support them natively. Hardware without native support will either trigger an address-misaligned exception or handle it via a slow software trap handler, severely degrading performance. Therefore, explicitly aligning data is a critical best practice.

Data Alignment Directives

Depending on your assembler (typically GNU as / GAS), you use specific directives to control the location counter's alignment:

Directive	Type of Boundary	Example Usage	Description
.align n	2ⁿ bytes (log2)	.align 2	Aligns the next item to a 2² = 4-byte boundary
.p2align n	2ⁿ bytes (log2)	.p2align 3	Explicitly power-of-two aligns to a 2³ = 8-byte boundary
.balign n	n bytes (Absolute)	.balign 4	Aligns directly to a multiple of 4 bytes

Crucial Rule: Alignment directives apply to the location counter, so they must appear before the label containing your data, not after it.

Natural Alignment Overview

To optimize memory performance and prevent alignment exceptions, structural components should be spaced according to their base data size:

.section .data .balign 2 # Align to 2-byte boundary my_half: .half 0x1234 .balign 4 # Align to 4-byte boundary my_word: .word 0xABCDEF12 .balign 8 # Align to 8-byte boundary my_dword: .dword 0x1122334455667788

Stack Alignment

When writing assembly functions, data alignment also rules the stack. The standard RISC-V Calling Convention (ABI) dictates that the Stack Pointer (sp) must remain 16-byte aligned at all times.

When allocating memory on the stack frame, always round your allocation size up to the nearest multiple of 16.

# Allocating space on the stack frame addi sp, sp, -16 # Keep stack 16-byte aligned sw ra, 12(sp) # Save Return Address sw s0, 8(sp) # Save Frame Pointer # ... your function code ... lw ra, 12(sp) # Restore RA lw s0, 8(sp) # Restore S0 addi sp, sp, 16 # Deallocate ret

.balign Overview

The .balign assembly directive in RISC-V pads the current location counter to a specified byte boundary.

How .balign Works

Syntax: .balign expression [, expression [, expression]]

First argument (alignment): The byte boundary alignment required (e.g., 4 for 32-bit alignment, 8 for 64-bit alignment, or 16). Must be a power of two.

Second argument (fill value, optional): The fill byte used for padding. If omitted, the assembler uses zero or a default NOP instruction depending on whether it is padding code or data.

Third argument (max padding, optional): Maximum number of bytes to skip. If the distance to the next alignment boundary exceeds this value, no padding is applied.

Usage in RISC-V

Code/Instruction Alignment: Used to align functions, loop entry points, or jump targets to specific byte boundaries for performance or architectural requirements (e.g., .balign 4 or .balign 16).

Linker Relaxation Interaction: In RISC-V GNU toolchains, alignment directives like .balign often generate a R_RISCV_ALIGN relocation so the linker can dynamically adjust padding if instructions are compressed/relaxed later (e.g., swapping 32-bit instructions for 16-bit [RVC] compressed instructions).

Best Practice: The plain .align directive in RISC-V assembler is an alias for .p2align (power of two), which can cause confusion across architectures. Using .balign (byte alignment) explicitly specifies the exact byte count, making code more portable and predictable.