Control and Status Registers (CSRs)
In RISC-V assembly, frm stands for Floating-Point Rounding Mode. It is a 3-bit subfield within the fcsr (Floating-Point Control and Status Register).
When you write floating-point instructions in simulators like RARS (RISC-V Assembler and Runtime Simulator), you can handle rounding either statically (per instruction) or dynamically (using the frm register).
| Binary Code | Mnemonic | Meaning |
|---|---|---|
| 000 | RNE | Round to Nearest, ties to Even (Default RISC-V mode) |
| 001 | RTZ | Round Towards Zero (Truncation) |
| 010 | RDN | Round Down (Towards -infinity) |
| 011 | RUP | Round Up (Towards +inifinity) |
| 100 | RMM | Round to Nearest, ties to Max Magnitude |
| 101–110 | Reserved for future use | |
| 111 | DYN | Dynamic (Uses the mode currently active in the frm register) |
Static Rounding (Per-Instruction)
You can append a specific rounding mode mnemonic directly to your floating-point instruction. This overrides whatever is inside the frm register for that specific execution.
Dynamic Rounding (Default Behavior)
If you do not specify a rounding mode suffix, RARS defaults to using dyn, which tells the processor to look at the global frm field in the fcsr.