RISC-V Assembly Language - Decimal Floating-Point

Note:Decimal floating-point is not part of the IEEE standards.

Decimal Floating Point (L extension) is a tentative standard RISC-V extension for base-10 representations (decimal32, decimal64, decimal128), and it is not supported in RARS.

"L" Standard Extension for Decimal (pdf)

Decimal Floating-Point, Version 0.0

  1. Standard DFP Interchange Format

    The draft standard defined three main widths for exchanging data, which match modern C/C++ types (such as _Decimal32, _Decimal64, and _Decimal128).

    Format
    Name
    Total
    bits
    Significant
    Range
    Exponent
    Range
    PurposeC-Type
    decimal32 32 bits 7 decimal
    digits
    (-95) to (+96) Storage economy(rarely used for arithmetic)
    decimal64 64 bits 16 decimal
    digits
    (-383) to (+384) Standard Precision(_Decimal64)
    decimal128 128 bits 34 decimal
    digits
    (-6143) to (+6144) Extended Precision(_Decimal128)

  2. Encoding the Significant (DPD vs. BID)

    Because computers are fundamentally binary, saving base-10 digits efficiently into binary bits required a new approach. The standard allows two encoding schemes:

    • Densely Packed Decimal (DPD): Compresses groups of 3 decimal digits into 10 bits (whereas standard BCD would require 12 bits). This is the preferred standard for IBM hardware (z/Architecture and POWER processors).

    • Binary Integer Decimal (BID): Encodes the significant directly as a massive standard binary integer. This scheme is favored by software-based math libraries and Intel/AMD architectures.

    Both encodings store the exact same mathematical value and range; they only differ in how the bits are organized on the chip.

  3. Special Values and States

    Just like binary floating-point, the decimal standard reserves specific bit patterns for boundary cases:

    • Signed Zeros: Both (+0.0) and (-0.0) are supported.

    • Infinities: (+infty) and (-infty) handle overflow conditions.

    • NaN (Not a Number): Divided into Quiet NaNs (qNaN) and Signaling NaNs (sNaN) to represent invalid operations.